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| Clearance |
| Minimum Security Clearance Requirement: Single Scope Background Investigation (TS/SSBI) |
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Job Location |
Geographic Location: Melbourne, Florida 32901
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Job Location: On-Site/Office
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Travel Requirement: Not Specified
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| To Apply |
| Apply for Job: There are two steps to apply for this job. First, click here to create a free FederalJobs.net account and post your resume. Then, click here to submit your resume via email to this employer. |
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| FPGA / VHDL Signal Processing Engineer |
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Yoh IT has a contract-to-hire opportunity for an FPGA / VHDL Signal Processing Engineer to join our customer in Melbourne, FL.
This consultant will be developing a FPGA system. Consultant will need to develop VHDL code for a front end filter. They will be building a signal processing UHDL.
Requirements:
• Must have years experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices.
• Equivalent experience in ASIC design will also receive consideration.
• Expertise in VHDL development languages.
• Expertise in simulation, synthesis, and placement software tools such as ModelSim, Synplicity, Xilinx ISE and/or Altera Quartus development tool sets.
• Expertise in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices.
• Familiarity with Clearcase code revision tool is only a plus.
• Familiarity with C/C++ and Matlab/Simulink is also a plus.
• Special Requirements: Due to the nature of this position requires consultant to already have a Department of Defense security clearance. Clearance must be specifically a TS/SBBI.
Discover all that’s possible with Yoh IT. Apply now.
Yoh, a Division of Day & Zimmermann, delivers talent and workforce solutions in Aerospace & Defense, Engineering, Information Technology, Life Sciences and Telecommunications, helping clients address complexities of managing cost, risk, quality and value of the entire workforce. Founded in 1940, Yoh is headquartered in Philadelphia, PA and operates from 75 locations. |
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Career Level: 10+ yrs experience
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Type: Full Time Contractor/Consultant
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Industry/Job Category: FPGA / VHDL Signal Processing Engineering
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Compensation |
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Total Compensation: Unspecified hourly wage. |
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